1. Field of the Invention
The present invention relates to a device configured to arbitrate bus accesses made by a plurality of modules and a method for controlling the device.
2. Description of the Related Art
When a bus-use request is transmitted from each of a plurality of bus masters which access a memory bus connected to a dynamic random access memory (DRAM), an arbiter configured to arbitrate the bus accesses gives the right to use the memory bus to one of the bus masters, so as to control (arbitrate) the bus-use right. In the past, the bus-use-right priority has been given to the bus masters from a hardware point of view. Therefore, when the bus-use requests are transmitted from the plurality of bus masters at the same time, the bus arbiter transmits a bus-use-permission signal to a predetermined one of the bus masters, which is typically the bus master with a high priority. Subsequently, the bus-use right is given to the bus master with the high priority. The above-described technology is disclosed in Japanese Patent Laid-Open No. 09-062579, for example.
Accordingly, if the bus-use request is frequently transmitted from the bus master with the high priority, the rate at which the bus master with the high priority obtains the bus-use right increases. In that case, it becomes difficult for the bus master with a low priority to obtain the bus-use right.
Therefore, by restricting the reception of the next bus-use request until the bus-use right is given to each of the bus-use requests that were received, the bus master with the low priority can obtain the bus-use right. However, when a large number of the bus masters transmit the bus-use requests, the number of accesses made by the bus master with the high priority becomes almost the same as that of accesses made by the bus master with the low priority.
Further, if the bus-use right is moved from one bus master to another bus master at frequent intervals when a burst-transfer-capable bus and/or the memory bus connected to the DRAM or the like is used, overhead for the address setting increases and the bus-use efficiency decreases.
Further, when the arbitration of the bus-use right is exclusively performed by a single arbiter, the arbitration processing becomes complicated due to an increased number of bus masters, the circuit size increases, and the high-speed operability of the bus decreases.